The present invention relates to a process for manufacturing a semiconductor device and, more particularly, to a process suited for mass production of a highly integrated semiconductor device.
Semiconductor devices of various forms have been developed to meet recent demands in the electronics field towards size and weight reduction, speed increase, and improvement of functional operations of the devices. The semiconductor device comprises a package and a semiconductor chip (hereinafter, also referred to as a chip) contained in the package. The chip has been integrated higher and higher, and such a highly integrated semiconductor chip increases the number of terminals thereon. In addition, there have been severe demands on the semiconductor chips towards the possible reduction in size. The terminal-to-terminal pitch should thus be reduced to meet these demands or requirements for the semiconductor devices. A semiconductor device having a high terminal count can be obtained by inner lead bonding or by area array bonding. The inner lead bonding and the area array bonding are expected to be inevitable for the field of the semiconductors.
The inner lead bonding (ILB) is used to make electrical contact between the chip and the leads within the package. Various bonding technologies are available to achieve this inner lead bonding. Wire bonding is the most extensively used electrical interconnection process. In this process, fine wires are used to make electrical contact between the bonding pads on the chip and the corresponding leads on the package. The wire diameter is typically from 20 to 30 micrometers. Wire bonding techniques include thermocompression bonding, ultrasonic bonding, and thermosonic bonding.
The use of the fine wires limits the number of interconnections available in one package. The recent demands for the semiconductor devices with a high terminal count thus causes a problem of poor connections between the wire and the bonding pads. Considering this fact, the wire bonding has been replaced with wireless bonding. The wireless bonding is also called gang bonding, with which all bumps on the electrode pads are bonded simultaneously to the leads. Wireless bonding techniques include tape automated bonding (TAB) and flip-chip bonding. The TAB is also referred to as tape carrier bonding.
In the TAB technique, a laminated tape of gold-plated copper foil etching in the form of leads is bonded to the bumps on the electrode pads. The elimination of the wire bonding is advantageous from viewpoints of size reduction and highly integrated packaging of the device. On the other hand, the flip-chip bonding requires to make a raised metallic bump of solder on the chip. The chip is then inverted and bonded face down to the substrate interconnection pattern. This process lends itself to production of semiconductor devices with a high terminal count and a smaller pitch. In addition, this technique is also advantageous to provide a fast, low-noise semiconductor device with the short length of the interconnections.
The TAB and flip-chip bonding techniques use the bumps provided between the chip and the package to make electrical interconnection between them. These techniques are disclosed in, for example, Japanese Patent Laid-open Nos. 5-129366 and 6-77293.
As mentioned above, the film carrier semiconductor device disclosed in these laid-open publications uses the bumps for the electrical interconnection between the chip and the carrier film. There is another film carrier semiconductor device in which the electrical interconnection between the chip and the carrier film is achieved without using the bumps. The semiconductor chip and the carrier film are electrically connected during the assembly process. The bumps are used only for the purpose of connecting the film carrier semiconductor device with, for example, a circuit board or a mounting board. The film carrier semiconductor device of the type described comprises a semiconductor chip and a carrier film. Contact pads are provided on the semiconductor chip at one side thereof. The contact pads are arranged along the periphery of the semiconductor chip. Interconnecting layers are provided on the carrier film. The carrier film is also provided with through-holes and openings formed therein. The openings are formed at the position corresponding to the contact pads (chip electrodes).
A conventional process for manufacturing a semiconductor device is described first for the purpose of facilitating the understanding of the present invention. In this event, description is made on a process for manufacturing a film carrier semiconductor device. A wafer, which comprises a number of chip sections each having chip electrodes formed thereon, is covered with a passivating film by using a well-known technique. After the formation of the passivating film, the chip electrodes are exposed to the atmosphere. The chip sections are then separated from each other into individual chips along scribe lines by means of a known dicing technique using a dicing saw. The semiconductor chip so obtained is prepared along with a carrier film and an adhesion film. The adhesion film is positioned relative to the semiconductor chip and placed thereon. The carrier film and the semiconductor chip are subjected to heat and pressure to adhere them through the adhesion film. The carrier film is then cut along the edges of the chip by means of any adequate method. Next, bump electrodes (solder bump) are formed on corresponding outer chip electrodes arranged on the carrier film.
Semiconductor devices so obtained may find various applications in the electronics, electrical, and other fields. For example, semiconductor devices may be used for memories and drivers for a liquid crystal display. Such applications are suited for mass-production of the semiconductor device. However, the above mentioned manufacturing process has a certain limitation on the number of chips obtained per unit time because the operation should be made for each chip. Recent demands for smaller memories or drivers have reduced the size of the semiconductor device itself. Accordingly, it is necessary to conduct the operations such as the inner lead bonding and the formation of the bumps for each small chip. Such operation is so elaborate and somewhat troublesome because the semiconductor chip is relatively small. It is thus difficult to position the carrier film positively or with a high accuracy. The elaborate operation is also associated with the reliability of the electrical interconnection between the semiconductor chip and the carrier film. In other words, there may be trouble in the interconnection between the semiconductor chip and the carrier film as well as the adhesion of the individual components. In this respect, a batch process may be more effective than the conventional process for the mass-production of the semiconductor device, in which most operations are conducted on chip sections of a wafer. In this process, the bump electrodes are formed on the chip sections of the wafer which are not separated from each other into the individual chips.
Such a method is disclosed in, for example, U.S. Pat. No. 5,137,845, issued to Lochon et al. This method has developed by IBM Corporation and is applicable to the manufacturing of bump electrodes for semiconductor chips that are suitable for Controlled Collapse Chip Connection (C4) or flip-chip technique. In this method, a barrier metal is deposited on aluminum chip electrodes, on which bump electrodes are deposited for a terminal contact. The resultant wafer is, however, directed to the application as it is. In other words, this patent is not for a wafer to be divided into semiconductor chips. There is no disclosure of the separation of the wafer nor the disclosure about the position of the interconnection, chip electrodes, and bump electrodes to avoid the breakage of them upon dicing. In addition, the bump electrodes in the above mentioned conventional semiconductor devices are formed on the corresponding chip electrodes. The formation of the bumps on the electrodes is, however, difficult or even impossible by the practical consideration to meet recent demands on the semiconductor chips towards the possible reduction in size with a higher terminal count and a smaller pitch.
This problem may be solved by means of using a multi-layered electrode structure of the semiconductor device which allows the distribution of the solder pads on the entire surface of the semiconductor chip. Such a structure is, however, complex and difficult to be manufactured. In addition, the multi-layered electrode significantly affects the configuration of the chip surface. A larger number of layers may sometimes make the surface irregular.
Accordingly, an object of the present invention is to provide a process for manufacturing a semiconductor device having bump electrodes formed at different positions from chip electrodes, which is suited for mass-production.
Another object of the present invention is to provide a process for manufacturing a semiconductor device having a good thermal stress resistance.
Yet another object of the present invention is to provide a process for manufacturing a semiconductor device having a good moisture resistance.